For example, in a manufacturing process of a semiconductor device in a multilayer wiring structure, a resist coating treatment of applying a resist solution, for example, onto a semiconductor wafer (hereinafter, referred to as a “wafer”) to form a resist film, exposure processing of exposing a predetermined pattern to the resist film, a developing treatment of developing the exposed resist film and so on are performed in sequence to thereby form a predetermined resist pattern on the wafer. Using the resist pattern as a mask, an etching treatment for the wafer is performed, and then a removal treatment of the resist film and so on are performed to form a predetermined pattern on the wafer. The process of forming the predetermined pattern in a predetermined layer is repeatedly performed multiple rounds to manufacture the semiconductor device in a multilayer wiring structure.
Incidentally, in the case where the predetermined pattern is repeatedly formed on the wafer as described above, the surface to which the resist solution is applied needs to be flat in order to form a resist film in an (n+1)-th layer at an appropriate height after a predetermined pattern is formed in an n-th layer.
Hence, conventionally, an organic film is formed on the predetermined pattern on the wafer and its surface is planarized. The formation of the organic film is performed by applying an organic material onto the wafer, heating the applied organic material to form an organic film, and etching back the organic film by, for example, a dry etching method (reactive ion etching method) to remove the surface of the organic film (Patent Document 1). Further, as the organic film, for example, an SOC (Spin On Cap) film, an SOG (Spin On Glass) film or the like is used.